VTC2012 - A top level integration frontend entry tool
For Verilog/VHDL engineers working in ASIC, FPGA or CPLD field.
VTC (Verilog/VHDL Tool - Connector) 2012 is a GUI-based EDA frontend entry tool for HDL structural integration. Users can directly drag wires to connect cell modules in the full function interface, ensuring the work is done correctly and efficiently.
With VTC2012, you can quickly build the HDL code's framework, by top-down or bottom-up flow, and with the document file.
- Full mixed bidirectional Verilog and VHDL support
- Automatically instantiate cell modules or entities
- Full function dynamic graphic user interface
- Automatic port connection driven by Smart Link technology
- User defined naming rules for instance and wire
- Bus combination and inout construction
- Generate Verilog/VHDL connection module automatically
- Visually adjustment of HDL code format
- Output formatted file list
- Generate test fixture by Verilog and VHDL
- And more...
VTM2012 - A table based interface editor
VTM is intended to be a table based edit tool for HDL module's interface definition, and unify the process of HDL coding and document writing.