Topweaver Anydivider 1.1

User's Guide

December 2006

Chinese Version

Overview

How to use

Implementation

Revision history

Copyright


Overview

DLL/PLL resources provide a good way to frequency synthesis. But sometimes people writes their own HDL code to fulfill the clock division function, for special multiply/divide values, adjustable duty cycle or other requirements that can hardly be achieved by using a DLL/PLL.

Topweaver Anydivider (TAD) is a GUI based EDA tool to generate a divided output clock (frequency = Fout) based on an input clock (frequency = Fin), without a DLL/PLL. The waveform of the output clock can be either from automatical calculation or from visual adjustment.

Fout=Fin * M / N. (1<=M<=N, 1<=N<=32700)

This version of TAD does not support M>N, though it is possible to get a Fout (M>N) without a DLL/PLL under dedicated backend constraint.

Proper backend constraint, advanced synthesis and PAR tool may be required to achieve better performance.

In fact TAD can be used in other situations, for example a flag signal of any time slot.

Topweaver Anydivider is a member of Topweaver tools family.

 


 

How to use

Auto Mode

Enter the wanted value in the Output Frequency, Reset Control, Duty Cycle and Signal Name section.

Move the duty cycle track bar to a suitable position, while watching the diagram.

View the performance report.

Use the file menu or toolbar command to generate the Verilog HDL source code.

Manual Mode

Make sure "Enable Ratio adjustment" is checked.

In the waveform of "Clock Out", drag an edge, a pulse or any selected segment. The diagram dynamically reflects the movement.

You can also scan all the possible cases by the "scan" command.


Implementation

Topweaver Anydivider can generate the HDL code based on two different implementation methods when using the negedge clock. The first is XOR of two registers, provided by Gabor on the newsgroup article (http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/be0ac835e148bf29/); the second is gated clock.
The following figure shows the difference of the two methods when generating a narrow pulse.

Figure: XOR and Gated Clock mehtods when generating a narrow pulse

When using the XOR method, the registers H and L cannot recover from a error state automatically, so an optional error indicator is provided.


Revision history

The following table shows the revision history for Topweaver Anydivider.

Date
Version
Revision
Dec 2, 2006
1.0
Initial Topweaver Anydivider release.
Dec 17, 2006
1.1

Add XOR implementation method, provided by Gabor on the newsgroup article (http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/be0ac835e148bf29/).
Add scale mark function.
Some small improvements.

 


Copyright

Topweaver Anydivider 1.1

Topweaver Tools Family

Copyright (c) 2002-2006, Topweaver

Website: http://www.topweaver.com

All rights reserved.